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EM44DM0888LBA feb. 2012 1/29 www.eorex.com revision history revision 0.1 (feb. 2011) -first release. revision 0.2 (jan.2013) -add speed 1066.
EM44DM0888LBA feb. 2012 2/29 www.eorex.com 1gb (16m 8 bank 8) double data rate 2 sdram features ? jedec standard vdd/vddq = 1.8v 0.1v. ? all inputs and outputs are compatible with sstl_1 8 interface. ? fully differential clock inputs (ck, /ck) operati on. ? eight banks ? posted cas ? bust length: 4 and 8. ? programmable cas latency (cl): 6 & 7 ? programmable additive latency (al): 0, 1, 2, 3, 4, 5 & 6. ? write latency (wl) =read latency (rl) -1. ? read data strobe (rdqs) supported ? bi-directional differential data strobe (dqs). ? data inputs on dqs centers when write. ? data outputs on dqs, /dqs edges when read. ? on chip dll align dq, dqs and /dqs transition with ck transition. ? dm mask write data-in at the both rising and fall ing edges of the data strobe. ? sequential & interleaved burst type available. ? off-chip driver (ocd) impedance adjustment ? on die termination (odt) ? auto refresh and self refresh ? 8,192 refresh cycles / 64ms ? 7.8us at average periodic refresh interval ? rohs compliance ? tras lockout supported ? high temperature self-refresh rate enable description the EM44DM0888LBA is a high speed double date rate 2 (ddr2) synchronous dram fabricated with ultra high performance cmos process containing 1,073,741,824 bits which organized as 16mbits x 8 banks by 8 bits. this synchronous device achieves high speed double-data-rate transfer rates of up to 1066 mt/sec (ddr2-1066) for general applications. the chip is designed to comply with the following k ey ddr2 sdram features: (1) posted cas with additive latency, (2) write latency = read latency -1, (3) off-chip driver (ocd) impedance adjustment and on die termination (4) normal and weak strength data output driver. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and / ck falling). all i/os are synchronized with a pair of bidirectional strobes (dqs and /dqs) in a source synchronous fashion. the address bus is used to convey row, column and bank address information in a /ras and /cas multiplexing style. the 1gb ddr2 devices operates with a single power supply: 1.8v 0.1v vdd and vddq. available package: fbga-60ball (with 0.8mm x 0.8mm ball pitch)
EM44DM0888LBA feb. 2012 3/29 www.eorex.com ordering information part no organization max. freq package grade pb EM44DM0888LBA-25f 128m x 8 t ck6 : ddr2-800 6-6-6 fbga-60b commercial free EM44DM0888LBA-187f 128m x 8 t ck7 : ddr2-1066 7-7-7 fbga-60b commercial free note: speed ( t ck *) is in order of cl-t rcd -t rp parts naming rule * eorex reserves the right to change products or sp ecification without notice.
EM44DM0888LBA feb. 2012 4/29 www.eorex.com pin assignment: top view 1 2 3 7 8 9 vdd nu/ rdqs vss a vssq dqs vddq dq6 vssq dm/rdqs b dqs vssq dq7 vddq dq1 vddq c vddq dq0 vddq dq4 vssq dq3 d dq2 vssq dq5 vddl vref vss e vssdl ck vdd cke we f ras ck odt ba2 ba0 ba1 g cas cs a10 a1 h a2 a0 vdd vss a3 a5 j a6 a4 a7 a9 k a11 a8 vss vdd a12 nc l nc a13 60ball fbga note: vddl and vssdl are power and ground for the d ll.
EM44DM0888LBA feb. 2012 5/29 www.eorex.com pin description (simplified) pin name function e8,f8 ck,/ck (system clock) ck and ck are differential clock inputs. all addres s and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck. output (read) data is referenc ed to the crossings of ck and ck (both directions of crossing). g8 /cs (chip select) all commands are masked when cs is registered high. cs provides for external rank selection on systems with multipl e ranks. cs is considered part of the command code. f2 cke (clock enable) cke high activates and cke low deactivates internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self- refresh operation (a ll banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit and for self-refresh entr y. cke is asynchronous for self-refresh exit. cke must be mai ntained high throughout read and write accesses. input buffers, excluding ck, /ck, odt and cke are disabled during power down. input b uffers, excluding cke are disabled during self-refresh. h8,h3,h7,j2, j8,j3,j7,k2, k8,k3,h2,k7, l2,l8 a0~a13 (address) provided the row address (ra0 ? ra13) for active co mmands and the column address (ca0-ca9) and auto precharge bit for read/write commands to select one location out of the memory a rray in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be pre charged, the bank is selected by ba0, ba1 & ba2. the address inputs also provide the op-code during mode register set commands. g2,g3,g1 ba0, ba1,ba2 (bank address) ba0 ? ba2 define to which bank an active, read, wri te or precharge command is being applied. bank address also determi nes if the mode register or extended mode register is to be accesse d during a mrs or emrs cycle. f9 odt (on die termination) odt (registered high) enables termination resistanc e internal to the ddr2 sdram. when enabled, odt is applied to each dq , udqs/udqs, ldqs/ldqs, udm, and ldm signal. the odt pin will be ignored if the extended mode register (emrs(1)) is programmed to disable odt. f7, g7, f3 /ras,/cas,/we (command inputs) /ras, /cas and /we (along with /cs) define the comm and being entered.
EM44DM0888LBA feb. 2012 6/29 www.eorex.com pin description (continued) b3,a2,b7,a8 rdqs,/rdqs , dqs,/dqs (data strobe) output with read data, input with write data. edge- aligned with read data, centered in write data. an rdqs option using dm pin can be enabled via the emrs(1) to simplify read timing. the data strobes dqs and rdqs may be used in single ended mode or paired with optional complimentary signals /dqs and /rdqs to provide differential pair signaling to the system d uring both reads and writes. an emrs(1) control bit enables or disables all complementary data strobe signals. b3 dm (data mask) dm is an input mask signal for write data. input da ta is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. althoug h dm pins are input only, the dm loading matches the dq and dqs l oading. dm is enabled by emrs command. c8,c2,d7,d3, d1,d9,b1,b9 dq0~7 (data input/output) data inputs and outputs are on the same pin. a1,l1,e9,h9/ a3,e3,j1,k9 vdd/vss (power supply/ground) vdd and vss are power supply for internal circuits. a9,c1,c3,c7, c9/a7,b2,b8, d2,d8 vddq/vssq (dq power supply/dq ground) vddq and vssq are power supply for the output buffe rs. e1/e7 vddl/vssdl (dll power supply/dll ground) vddl and vssdl are power supply for dll circuits e2 vref (reference voltage) sstl_1.8 reference voltage l3,l7 nc (no connection) no internal electrical connection is present.
EM44DM0888LBA feb. 2012 7/29 www.eorex.com absolute maximum rating symbol item rating units v in , v out input, output voltage -0.5 ~ +2.3 v v dd power supply voltage - 1 . 0 ~ + 2. 3 v v ddq power supply voltage -0.5 ~ +2.3 v v ddl dll power supply voltage -0.5 ~ +2.3 v t op operating temperature range commercial 0 ~ +70 c t stg storage temperature range - 55 ~ +1 0 0 c p d power dissipation 1 w note: caution exposing the device to stress above those l isted in absolute maximum ratings could cause permanent damage. the device is not mea nt to be operated under conditions outside the limits described in the operational sec tion of this specification. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. recommended dc operating conditions (t a =-0c ~+70c) symbol parameter min. typ. max. units v dd power supply voltage 1.7 1.8 1.9 v v ddl power supply for dll voltage 1.7 1.8 1.9 v v ddq power supply for i/o voltage 1.7 1.8 1.9 v v ref i/o reference voltage 0.49 v ddq 0.50v ddq 0.51 v ddq v v tt i/o termination voltage v ref -0.04 v ref v ref +0.04 v v id dc differential input voltage -0.3 - v ref -0.15 v v ih input logic high voltage v ref +0.125 - v ddq +0.3 v v il input logic low voltage -0.3 - v ref -0.125 v
EM44DM0888LBA feb. 2012 8/29 www.eorex.com recommended dc operating conditions (v dd =1.8v0.1v) symbol parameter test conditions -187(1066) -25(800) units max i dd1 operating current (note 1) iout = 0ma bl = 4, cl = cl(idd), al = 0 tck = tck(idd), trc = trc (idd) tras = trasmin(idd), trcd = trcd(idd) cke=high cs=high between valid commands address bus inputs are switching data pattern is same as idd4w 102 85 ma i dd2p precharge standby current in power down mode all banks idle tck = tck(idd), cke is low other control and address bus inputs are stable data bus inputs are floating 10 10 ma i dd2n precharge standby current in non-power down mode all banks idle all banks idle tck = tck(idd), cke is high, cs is high other control and address bus inputs are switching data bus inputs are switching 48 40 ma i dd3p active standby current in power down mode (a12=0) all banks open tck = tck(idd), cke is low other control and address bus inputs are stable data bus inputs are floating 36 30 ma i dd3p active standby current in power down mode (a12=1) 11 10 ma i dd3n active standby current in non-power down mode all banks open tck = tck(idd), tras = trasmax(idd) trp = trp(idd), cke is high cs is high between valid commands other control and address bus inputs are switching data bus inputs are switching 60 50 ma i dd4w operating current (burst mode) (note 2) all banks open, continuous burst writes bl = 4, cl = cl(idd), al = 0 tck = tck(idd), tras = trasmax(idd) trp = trp(idd), cke is high cs is high between valid commands address bus inputs are switching data bus inputs are switching 144 120 ma i dd4r 144 120 i dd5 refresh current (note 3) tck = tck(idd) refresh command at every trfc(idd) interval cke is high, cs is high between valid commands other control and address bus inputs are switching data bus inputs are switching 210 175 ma i dd6 self refresh current ck and ck at 0 v, cke 0.2 v other control and address bus inputs are floating, data bus inputs are floating 9 9 ma i dd7 operating current all bank interleaving reads iout = 0ma, bl = 4, cl = cl(idd) al = trcd(idd) - 1 x tck(idd) tck = tck(idd), trc = trc(idd) trrd = trrd(idd), tfaw = tfaw(idd) trcd = 1 x tck(idd), cke is high cs is high between valid commands address bus inputs are stable during deselects data pattern is same as idd4r 300 250 ma *all voltages referenced to vss. note 1: i dd1 depends on output loading and cycle rates . (cl=clmin, al=0) note 2: i dd4 depends on output loading and cycle rates . input signals switching note 3: min. of t rfc (auto refresh row cycle times) is shown at ac char acteristics.
EM44DM0888LBA feb. 2012 9/29 www.eorex.com recommended dc operating conditions (continued) symbol parameter test conditions min. max. units ioh output minimum source current *note2, 4, 5 -13.4 ma iol output minimum sink current *note3, 4, 5 +13.4 ma note1: the vddq of the device under test is referenced note2: vddq=1.7v, vout=1.42v note3: vddq=1.7v, vout=0.28v note4: the dc value of vref applied to the receiving devic e is expected to be set to vtt note5: after ocd calibration to 18 at tc=25 , vdd=vddq=1.8v input/output capacitance symbol parameter ddr2-800 ddr2-1066 units min max min max c ck input capacitance, ck & /ck 1.0 2.0 1.0 2.0 pf c dck input capacitance delta, ck & /ck - 0.25 - 0.25 pf c i input capacitance, all other pins 1.0 1.75 1.0 1.7 5 pf c di input capacitance delta, all other pins - 0.25 - 0 .25 pf c io i/o capacitance, dq,dm,dqs,/dqs 2.5 3.5 2.5 3.5 pf c dio i/o capacitance delta, dq,dm,dqs,/dqs - 0.5 - 0.5 pf
EM44DM0888LBA feb. 2012 10/29 www.eorex.com block diagram row add. buffer row decoder address register auto/ self refresh counter memory array s/ a & i/ o gating col. decoder col. add. buffer mode register set col add. counter burst counter dqm control data in data out dio a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a 10 a 11 a12 ba 0 ba1 timing register ck cke /cs / ras / cas /we dm dm /ck dqs dqs receiver write fifo driver dqs generator dll ck, /ck clk, /clk a13 ba2
EM44DM0888LBA feb. 2012 11/29 www.eorex.com ocd default setting table parameter min. typ. max. units output impedance 12.6 18 23.4 pull-up / pull-down mismatch 0 - 4 output slew rate 1.5 - 5.0 v/ns output impedance step size for ocd calibration 0 - 1.5 ac operating test conditions (v dd =1.8v0.1v) symbol parameter value units v swing (max.) input signal maximum peak to peak swing 1.0 v slew input signal minimum slew rate 1.0 v/ns v ref input reference level 0.5*v ddq v ac operating test conditions symbol parameter min. max. units v id ac differential input voltage 0.5 v ddq v v ix ac differential cross point input voltage 0.5*v ddq -0.175 0.5*v ddq +0.175 v v ox ac differential cross point output voltage 0.5*v ddq -0.125 0.5*v ddq +0.125 v v ih input logic high voltage v ref +0.200 v ddq +v peak v v il input logic high voltage v ssq -v peak v ref -0.200 v
EM44DM0888LBA feb. 2012 12/29 www.eorex.com ac operating test characteristics (v dd =1.8v0.1v) symbol parameter -187 (ddr2-1066) -25 (ddr2-800) units min. max. min. max. t ac dq output access from clk,/clk -350 350 -400 400 p s t dqsck dqs output access from clk,/clk -350 350 -350 350 ps t cl ,t ch cl low/high level width 0.48 0.52 0.48 0.52 t ck t ck clock cycle time 1.875 8 2.5 8 ns t ds dq and dm setup time 0 - 50 - ps t dh dq and dm hold time 75 - 125 - ps t dipw dq and dm input pulse width for each input 0.35 - 0.35 - t ck t hz data out high impedance time from clk,/clk - t ac (max) - t ac (max) ns t lz (dq) dq low impedance time from clk,/clk 2*t ac (min) t ac (max) 2*t ac (min) t ac (max) ns t lz (dqs) dqs,/dqs low impedance time from clk,/clk t ac (min) t ac (max) t ac (min) t ac (max) ns t dqsq dqs-dq skew for associated dq signal - 175 - 200 ps t qhs data hold skew factor - 250 - 300 ps t dqss write command to first latching dqs transition -0.25 0.25 -0.25 0.25 t ck t dqsl ,t dqsh dqs low/high input pulse width 0.35 - 0.35 - t ck t dsl ,t dsh dqs input valid window 0.20 - 0.20 - t ck t mrd mode register set command cycle time 2 - 2 - t ck t wpres write preamble setup time 0 - 0 - ns t wpre write preamble 0.35 - 0.35 - t ck t wpst write postamble 0.4 0.6 0.4 0.6 t ck t is address/control input setup time (fast slew rate) 125 - 175 - ps t ih address/control input hold time (fast slew rate) 200 - 250 - ps t rpre read preamble 0.9 1.1 0.9 1.1 t ck
EM44DM0888LBA feb. 2012 13/29 www.eorex.com ac operating test characteristics (continued) (vdd=1.8v0.1v) symbol parameter -187 (ddr2-1066) -25 (ddr2-800) units min. max. min. max. t rpst read postamble 0.4 0.6 0.4 0.6 t ck t ras active to precharge command period 45 70k 45 70k ns t rc active to active command period 57.5 - 57.5 - ns t rfc auto refresh row cycle time 127.5 - 127.5 - ns t rcd active to read or write delay 12.5 - 12.5 - ns t rp precharge command period 12.5 - 12.5 - ns t rrd active bank a to b command period 7.5 - 7.5 - ns t ccd column address to column address delay 2 - 2 - t ck t wr write recover time 15 - 15 - ns t dal auto precharge write recovery + precharge time t rp + t wr - t rp + t wr - ns t xard exit active power-down mode to read command (fast exit) 3 - 2 - t ck t xards exit active power-down mode to read command (slow exit) 10-al - 8-al - t ck t xp exit precharge power-down to any non-read command 3 - 2 - t ck t wtr internal write to read command delay 7.5 - 7.5 - ns t rtp internal read to precharge delay 7.5 - 7.5 - ns t xsnr exit self refresh to non-read command t rfc +10 - t rfc +10 - ns t xsrd exit self refresh to read command 200 - 200 - t ck t refi average periodic refresh interval - 7.8 - 7.8 us t cke cke minimum pulse width 3 - 3 - t ck t faw four active to row active delay (same bank) 35 35 ns t oit ocd drive mode output delay 0 12 0 12 ns
EM44DM0888LBA feb. 2012 14/29 www.eorex.com ac operating test characteristics (continued) (vdd=1.8v0.1v) symbol parameter speed 800 units min. max. t aond odt turn-on delay 2 2 t ck t aofd odt turn-off delay 2.5 2.5 t ck t aon odt turn-on (note1) t ac(min.) t ac(max) + 0.7 ns t aof odt turn-off (note2) t ac(min.) t ac(max) + 0.6 ns t aonpd odt turn-on in power-down mode t ac(min.) +2 2*t ck + t ac(max) +1 ns t aofpd odt turn-off in power-down mode t ac(min.) +2 2.5*t ck + t ac(max) +1 ns t anpd odt to power-down mode entry latency 3 - t ck t axpd odt power-down exit latency 8 - t ck (vdd=1.8v0.1v) symbol parameter speed 1066 units min. max. t aond odt turn-on delay 2 2 t ck t aofd odt turn-off delay 2.5 2.5 t ck t aon odt turn-on (note1) t ac(min.) t ac(max) + 2.575 ns t aof odt turn-off (note2) t ac(min.) t ac(max) + 0.6 ns t aonpd odt turn-on in power-down mode t ac(min.) +2 2*t ck + t ac(max) +1 ns t aofpd odt turn-off in power-down mode t ac(min.) +2 2.5*t ck + t ac(max) +1 ns t anpd odt to power-down mode entry latency 2.5 - t ck t axpd odt power-down exit latency 11 - t ck note 1: odt turn on time min is when the device leaves hig h impedance and odt resistance begins to turn on. odt turn on time max is when the odt resis tance is fully on. both are measure from t aond . note 2: odt turn off time min is when the device starts to turn off odt resistance odt turn off time max is when the bus is in high impedance. both are meas ured from t aofd .
EM44DM0888LBA feb. 2012 15/29 www.eorex.com simplified state diagram
EM44DM0888LBA feb. 2012 16/29 www.eorex.com 1. command truth table command symbol cke /cs /ras /cas /we ba0 ~ ba2 a10 a12~a0 n-1 n device deselect desl h x h x x x x x x no operation nop h x l h h h x x x read read h h l h l h v l v read with auto pre-charge reada h h l h l h v h v write writ h h l h l l v l v write with auto pre-charge writa h h l h l l v h v bank activate act h h l l h h v v v pre-charge select bank pre h h l l h l v l x pre-charge all banks pall h h l l h l x h x (ext.) mode register set emrs h h l l l l v* v v auto refresh ref h h l l l h x x x self refresh entry self h l l l l h x x x power down entry pden h l h x x x x x x h l l h h h x x x power down exit pdex l h h x x x x x x l h l h h h x x x h = high level, l = low level, x = high or low leve l (don't care), v = valid data input * please refers to the mrs, emrs(1) & emrs(2) s etting 2. cke truth table item command symbol cke /cs /ras /cas /we addr. n-1 n any state *note1 - h h v v v v v all bank idle self refresh entry self h l l l l h x self refresh self refresh exit nop l h l h h h x desl l h h x x x x all bank idle active or precharge power down entry desl h l h x x x x nop h l l h h h x power down power down exit desl l h h x x x x nop l h l h h h x power down maintain power down - l l x x x x x self refresh maintain self refresh - l l x x x x x h = high level, l = low level, x = high or low leve l (don't care) note1: must be legal commands as defined in the command t ruth table. and any state other than list above.
EM44DM0888LBA feb. 2012 17/29 www.eorex.com 3. operative command table current state /cs /r /c /w addr. command action h x x x x desl nop l h h h x nop nop l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa illegal (note 1) idle l l h h ba/ra act bank active,latch ra l l h l ba, a10 pre/prea nop (note 3) l l l h x ref/self auto/self refresh (note 4) l l l l op-code, mode-add mrs/emrs(1)(2) mode register h x x x x desl nop l h h h x nop nop l h l h ba/ca/a10 read/reada begin read,latch ca, determine auto-precharge bank active l h l l ba/ca/a10 writ/writa begin write,latch ca, determine auto-precharge l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea precharge/precharge all l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h x x x x desl row active(continue burst to end) l h h h x nop row active(continue burst to end) l h l h ba/ca/a10 read/reada burst interrupt read l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h x x x x desl write recovering (continue burst to end) l h h h x nop write recovering (continue burst to end) l h l h ba/ca/a10 read/reada illegal (note 1) write l h l l ba/ca/a10 writ/writa burst interrupt l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) l l l l op-code, mrs/emrs(1)(2) illegal (note 1)
EM44DM0888LBA feb. 2012 18/29 www.eorex.com 3. operative command table (continued) current state /cs /r /c /w addr. command action h x x x x desl precharging (continue burst to end) l h h h x nop precharging (continue burst to end) l h l h ba/ca/a10 read/reada illegal (note 1) read with ap l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/a10 act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) write with ap h x x x x desl write recover with auto precharge (continue burst to end) l h h h x nop write recover with auto precharge (continue burst to end) l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) pre-charging h x x x x desl nop(idle after trp) l h h h x nop nop(idle after trp) l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea nop(idle after trp) (note 3) l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) row activating h x x x x desl nop(row active after trcd) l h h h x nop nop(row active after trcd) l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h = high level, l = low level, x = high or low leve l (don't care), ap = auto pre-charge
EM44DM0888LBA feb. 2012 19/29 www.eorex.com 3. operative command table (continued) current state /cs /r /c /w addr. command action h x x x x desl nop (enter bank active after twr) l h h h x nop nop (enter bank active after twr) l h l h ba/ca/a10 read illegal (note 1) write l h l l ba/ca/a10 writ/writa new write, determine ap recovering l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) refreshing h x x x x desl nop(idle after t rfc ) l h h h x nop nop(idle after t rfc ) l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h = high level, l = low level, x = high or low leve l (don't care), ap = auto pre-charge note 1: illegal to bank in specified states; function may be legal in the bank indic ated by bank address (ba), depending on the state o f that bank. note 2: must satisfy bus contention, bus turn around, and/ or write recovery requirements. note 3: nop to bank precharging or in idle state.may precha rge bank indicated by ba. note 4: illegal of any bank is not idle.
EM44DM0888LBA feb. 2012 20/29 www.eorex.com 4. command truth table for cke current state c ke /cs /r /c /w addr. action h x x x x x x invalid l h h x x x x exist self-refresh l h l h h h x exist self-refresh self refresh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain self refresh) h x x x x x x invalid l h h x x x x exist power down both bank l h l h h h x exist power down precharge l h l h h l x illegal power down l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain power down) h h x x x x x refer to function true table h l h x x x x enter power down mode (note 3) h l l h h h x enter power down mode (note 3) h l l h h l x illegal all banks idle h l l h l x x illegal h l l l h h ra row active/bank active h l l l l h x enter self-refresh (note 3) h l l l l l op-code mode register access h l l l l l op-code special mode register access l x x x x x x refer to current state any state other than listed above h h x x x x x refer to command truth table h = high level, l = low level, x = high or low leve l (don't care) notes 1: after cke?s low to high transition to exist self re fresh mode.and a time of t rc (min) has to be elapse after cke?s low to high transition to issue a new command . notes 2: cke low to high transition is asynchronous as if re starts internal clock. notes 3: power down and self refresh can be entered only fro m the idle state of all banks. 5. bank selection signal table bank\signal ba0 ba1 ba2 bank0 l l l bank1 h l l bank2 l h l bank3 h h l bank4 l l h bank5 h l h bank6 l h h bank7 h h h note: h:vih, l:vil
EM44DM0888LBA feb. 2012 21/29 www.eorex.com initialization the following sequence is required for power-up and initialization and is shown in below figure: 1. apply power and attempt to maintain cke below 0. 2 * vddq and odt at a low state (all other inputs m ay be undefined). to guarantee odt off, vref must be vali d and a low level must be applied to the odt pin. - vdd, vddl and vddq are driven from a single power converter output, and vtt is limited to 0.95 v max , and vref tracks vddq/2 or - apply vdd before or at the same time as vddl; app ly vddl before or at the same time as vddq; - apply vddq before or at the same time as vtt & vr ef. at least one of these two sets of conditions mu st be met. 2. start clock (ck, /ck) and maintain stable power and clock condition for a minimum of 200 s. 3. apply nop or deselect commands & take cke high. 4. wait minimum of 400ns, then issue a precharge-al l command. 5. issue reserved command emrs(2) or emrs(3). 6. issue emrs(1) command to enable dll. (a0=0 and b a0=1 and ba1=0) 7. issue mrs command (mode register set) for "dll r eset". (a8=1 and ba0=ba1=0) 8. issue precharge-all command. 9. issue 2 or more auto-refresh commands. 10. issue a mrs command with low on a8 to initializ e device operation. (without resetting the dll) 11. at least 200 clocks after step 8, execute ocd c alibration (off chip driver impedance adjustment). if ocd calibration is not used, emrs ocd default command ( a9=a8=a7=1) followed by emrs(1) ocd calibration mode exit command (a9=a8=a7=0) must be issued with other parameters of emrs(1). 12. the ddr2 sdram is now initialized and ready for normal operation.
EM44DM0888LBA feb. 2012 22/29 www.eorex.com mode register definition mode register set the mode register stores the data for controlling t he various operating modes of ddr2 sdram which cont ains addressing mode, burst length, /cas latency, wr (wr ite recovery), test mode, dll reset and various ven dor?s specific opinions. the defaults value of the register is not defined, so the mode register must be written after power up for proper ddr2 sdram operation. the mode register is written by asserting low on /cs, /ras, /cas, /we and ba0/1. the state of the address pins a0-a12 in the same cy cle as /cs, /ras, /cas, /we and ba0/1 going low is written in the mode register. two clock cycles are requested to complete the writ e operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operating as long a s all banks are in the idle state. the mode register is divided into various fields de pending on functionality. the burst length uses a0- a2, addressing mode uses a3, /cas latency (read latency from column address) uses a4-a6. a7 is used for te st mode. a8 is used for ddr reset. a9 ~ a11 are used f or write recovery time (wr), a7 must be set to low for normal mrs operation. with address bit a12 two powe r-down modes can be selected, a ?standard mode? and a ?low-power? power-down mode.
EM44DM0888LBA feb. 2012 23/29 www.eorex.com address input for mode register set note1. active power down exit time?s fast exit (a12 =0) use t xard and slow exit (a12=1) use t xards. note2. a13 is reserved for future use. note3. ba2 is reserved for future use
EM44DM0888LBA feb. 2012 24/29 www.eorex.com burst type (a3) burst length a2 a1 a0 sequential addressing interleave addressing 4 x 0 0 0 1 2 3 0 1 2 3 x 0 1 1 2 3 0 1 0 3 2 x 1 0 2 3 0 1 2 3 0 1 x 1 1 3 0 1 2 3 2 1 0 8 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 *page length is a function of i/o organization and column addressing write recovery wr (write recovery) is for writes with auto-prechar ge only and defines the time when the device starts pre-charge internally. wr must be programmed to mat ch the minimum requirement for the analogue t wr timing. power-down mode active power-down (pd) mode is defined by bit a12. pd mode allows the user to determine the active power-down mode, which determines performance vs. p ower savings. pd mode bit a12 does not apply to precharge power-down mode. when bit a12 = 0, standa rd active power-down mode or ?fast-exit? active power-down mode is enabled. the t xard parameter is used for ?fast-exit? active power-dow n exit timing. the dll is expected to be enabled and running during th is mode. when bit m12 = 1, a lower power active power-down mode or ?slow-exit? active power-down mo de is enabled. the t xards parameter is used for ?slow-exit? active power-down exit timing. the dll can be enabled, but ?frozen? during active power-do wn mode since the exit-to-read command timing is relax ed. the power difference expected between pd ?normal? and pd ?low-power? mode is defined in the idd table.
EM44DM0888LBA feb. 2012 25/29 www.eorex.com extended mode register set emrs(1 ) the emrs (1) is written by asserting low on /cs, /r as, /cas, /we,ba1 and high on ba0 ( the ddr2 should be in all bank pre-charge with cke already prior to writing into the extended mode register. ) the ext ended mode register emrs(1) stores the data for enabling or disabling the dll, output driver strength, addit ive latency, ocd program, odt, dqs and output buffers d isable, rqds and rdqs enable. the default value of the extended mode register emrs(1) is not defined, therefore the extended mode register must be writte n after power-up for proper operation. the mode register se t command cycle time (t mrd ) must be satisfied to complete the write operation to the emrs(1). mode register c ontents can be changed using the same command and clock cycle requirements during normal operation wh en all banks are in pre-charge state. 0 a13 dll dic rtt additive latency rtt ocd program /dqs rdqs qoff a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 1 1 50 ohm 0 1 150 ohm 1 0 75 ohm 0 0 odt disable a2 a6 rtt weak (60%) normal (100%) output driver impedance control 1 1 1 reserved 0 1 1 6 1 0 1 5 0 0 1 4 1 1 0 3 0 1 0 2 1 0 0 1 0 0 0 0 a3 a4 a5 additive latency 1 disable 0 enable a10 /dqs 1 0 a11 1 1 1 (*2) 0 0 1 (*1) 0 0 1 0 0 0 0 0 a7 a8 1 1 0 1 1 0 0 0 ba0 ba1 1 0 a0 *1: when adjust mode is issued, al from previously set value m ust b e applied. *2: after setting to default, ocd mode needs to be exited by settin g a9 a7 to 000. refer to the section off - chip driver (ocd) impedance adjustment for detail information 1 0 ba0 ba1 1 1 50 ohm * 0 1 150 ohm 1 0 75 ohm 0 0 odt disable a2 a6 rtt 1 0 a1 1 1 1 reserved 0 1 1 6 1 0 1 5 0 0 1 4 1 1 0 3 0 1 0 2 1 0 0 1 0 0 0 0 a3 a4 a5 additive latency 1 disable 0 enable a10 /dqs 1 enable 0 disable a11 rdqs enable 1 disabled 0 enabled a12 qoff (output buffer) 1 1 1 ocd calibration default (*2) 0 0 1 adjust mode (*1) 0 1 0 drive (0) 1 0 0 drive (1) 0 0 0 ocd calibration mode exit a7 a8 a9 ocd calibration program 1 1 emrs(3) reserved 0 1 emrs(2) 1 0 emrs(1) 0 0 mrs ba0 ba1 mrs mode 1 disable 0 enable a0 dll * - - ba2 0 note1. for ddr2-1066, the ?rtt? must be set to 50 o hm (a2 = 1 & a6 = 1). note2. a13 is reserved for future use. note3. ba2 is reserved for future use.
EM44DM0888LBA feb. 2012 26/29 www.eorex.com output drive strength the output drive strength is defined by bit a1. nor mal drive strength outputs are specified to be sstl _18. programming bit a1 = 0 selects normal (100 %) drive strength for all outputs. programming bit a1 = 1 will reduce all outputs to a pproximately 60 % of the sstl_18 drive strength. this option is intended for the support of the ligh ter load and/or point-to-point environments. single-ended and differential data strobe signals emrs strobe function matrix signals a11 (/rdqs enable) a10 (/dqs enable) rdqs dm /rdqs dqs /dqs 0 (disable) 0 (enable) dm hi-z dqs /dqs differentia l dqs signal 0 (disable) 1 (disable) dm hi-z dqs hi-z single-end ed dqs signal 1 (enable) 0 (enable) rdqs /rdqs dqs /dqs differential dqs signal 1 (enable) 1 (disable) rdqs hi-z dqs hi-z single-en ded dqs signal output disable (qoff) under normal operation, the dram outputs are enable d during read operation for driving data qoff bit i n the emrs(1) is set to (0). when the qoff bit is set to 1, the dram outputs will be disabled. disabling the dram outputs allows users to measure idd currents during read operations, without including the output buff er current.
EM44DM0888LBA feb. 2012 27/29 www.eorex.com address input for extended mode register set emrs(2 )
EM44DM0888LBA feb. 2012 28/29 www.eorex.com on-die termination (odt) odt (on-die termination) is a new feature on ddr2 c omponents that allows a dram to turn on/off termination resistance for each udq, ldq, udqs, udq s, ldqs, ldqs, udm and ldm signal via the odt control pin for x16 configuration, where udqs and l dqs are terminated only when enabled in the emrs(1) by address bit a10 = 0. the odt feature is designed to improve signal integ rity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. the odt fu nction can be used for all active and standby modes. odt i s turned off and not supported in self- refresh mod e. odt function switch sw1 or sw2 is enabled by the odt pin. select ion between sw1 or sw2 is determined by ?rtt (nominal)? in emrs(1) address bits a6 & a2. target rtt = 0.5 * rval1 or 0.5 * rval2. the odt pin will be ignored if the emrs(1) is progr ammed to disable odt.
EM44DM0888LBA feb. 2012 29/29 www.eorex.com package description: 60ball-fbga solder ball: lead free (sn-ag-cu)

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